|author||Keshavamurthy, Anil S <email@example.com>||2007-10-21 16:41:49 -0700|
|committer||Linus Torvalds <firstname.lastname@example.org>||2007-10-22 08:13:18 -0700|
Intel IOMMU: Intel IOMMU driver
Actual intel IOMMU driver. Hardware spec can be found at: http://www.intel.com/technology/virtualization This driver sets X86_64 'dma_ops', so hook into standard DMA APIs. In this way, PCI driver will get virtual DMA address. This change is transparent to PCI drivers. [email@example.com: remove unneeded cast] [firstname.lastname@example.org: build fix] [email@example.com: fix duplicate CONFIG_DMAR Makefile line] Signed-off-by: Anil S Keshavamurthy <firstname.lastname@example.org> Cc: Andi Kleen <email@example.com> Cc: Peter Zijlstra <firstname.lastname@example.org> Cc: Muli Ben-Yehuda <email@example.com> Cc: "Siddha, Suresh B" <firstname.lastname@example.org> Cc: Arjan van de Ven <email@example.com> Cc: Ashok Raj <firstname.lastname@example.org> Cc: "David S. Miller" <email@example.com> Cc: Christoph Lameter <firstname.lastname@example.org> Cc: Greg KH <email@example.com> Signed-off-by: Adrian Bunk <firstname.lastname@example.org> Signed-off-by: Andrew Morton <email@example.com> Signed-off-by: Linus Torvalds <firstname.lastname@example.org>
Diffstat (limited to 'Documentation')
2 files changed, 103 insertions, 0 deletions
diff --git a/Documentation/Intel-IOMMU.txt b/Documentation/Intel-IOMMU.txt
new file mode 100644
@@ -0,0 +1,93 @@
+Linux IOMMU Support
+The architecture spec can be obtained from the below location.
+This guide gives a quick cheat sheet for some basic understanding.
+DMAR - DMA remapping
+DRHD - DMA Engine Reporting Structure
+RMRR - Reserved memory Region Reporting Structure
+ZLR - Zero length reads from PCI devices
+IOVA - IO Virtual address.
+ACPI enumerates and lists the different DMA engines in the platform, and
+device scope relationships between PCI devices and which DMA engine controls
+What is RMRR?
+There are some devices the BIOS controls, for e.g USB devices to perform
+PS2 emulation. The regions of memory used for these devices are marked
+reserved in the e820 map. When we turn on DMA translation, DMA to those
+regions will fail. Hence BIOS uses RMRR to specify these regions along with
+devices that need to access these regions. OS is expected to setup
+unity mappings for these regions for these devices to access these regions.
+How is IOVA generated?
+Well behaved drivers call pci_map_*() calls before sending command to device
+that needs to perform DMA. Once DMA is completed and mapping is no longer
+required, device performs a pci_unmap_*() calls to unmap the region.
+The Intel IOMMU driver allocates a virtual address per domain. Each PCIE
+device has its own domain (hence protection). Devices under p2p bridges
+share the virtual address with all devices under the p2p bridge due to
+transaction id aliasing for p2p bridges.
+IOVA generation is pretty generic. We used the same technique as vmalloc()
+but these are not global address spaces, but separate for each domain.
+Different DMA engines may support different number of domains.
+We also allocate gaurd pages with each mapping, so we can attempt to catch
+any overflow that might happen.
+If you encounter issues with graphics devices, you can try adding
+option intel_iommu=igfx_off to turn off the integrated graphics engine.
+Some exceptions to IOVA
+Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
+The same is true for peer to peer transactions. Hence we reserve the
+address from PCI MMIO ranges so they are not allocated for IOVA addresses.
+Boot Message Sample
+Something like this gets printed indicating presence of DMAR tables
+ACPI: DMAR (v001 A M I OEMDMAR 0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0
+When DMAR is being processed and initialized by ACPI, prints DMAR locations
+and any RMRR's processed.
+ACPI DMAR:Host address width 36
+ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000
+ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000
+ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000
+ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff
+ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff
+When DMAR is enabled for use, you will notice..
+PCI-DMA: Using DMAR IOMMU
+- For compatibility testing, could use unity map domain for all devices, just
+ provide a 1-1 for all useful memory under a single domain for all devices.
+- API for paravirt ops for abstracting functionlity for VMM folks.
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 6accd360da73..8157417724a8 100644
@@ -772,6 +772,16 @@ and is between 256 and 4096 characters. It is defined in the file
+ intel_iommu= [DMAR] Intel IOMMU driver (DMAR) option
+ Disable intel iommu driver.
+ igfx_off [Default Off]
+ By default, gfx is mapped as normal device. If a gfx
+ device has a dedicated DMAR unit, the DMAR unit is
+ bypassed by not enabling DMAR with this option. In
+ this case, gfx device will use physical address for
io7= [HW] IO7 for Marvel based alpha systems
See comment before marvel_specify_io7 in